Memories may detect a particular data value stored in a particular cell by presenting a signal, such as a signal TBUS, to a sense amplifier. The sense amplifier generally compares the voltage of the signal TBUS to a reference voltage. The reference voltage may be a global static reference voltage, a local static reference voltage or a dynamic reference voltage.
Referring to FIG. 1, a circuit 10 is shown illustrating a global reference voltage circuit that may be used in a memory. The circuit 10 generally comprises a memory array block 12, a column select block 14, a sense amplifier block 16 and a global reference block 18. The memory array block 12 includes a number of wordlines WL&lt;0:m&gt; that are shown presented to an input 20. The memory array block 12 presents a number of bitlines (i.e., BL&lt;0:n&gt;) to an input 22 of the column select block 14. A column address (i.e., COL&lt;0:x&gt;) is presented to an input 24 of the column select block 14. The column select block 14 presents the signal TBUS (i.e., TBUS&lt;0:y&gt;) to an input 26 of the sense amplifier block 16. The global reference block 18 presents a global reference signal (i.e., GREF) to an input 28 of the sense amplifier block 16. The sense amplifier block 16 presents a signal (i.e., SAOUT&lt;0:y&gt;) at an output 30 that represents the state of the data stored in the memory array block 12 at a particular location.
Referring to FIG. 2, a timing diagram of the various signals of FIG. 1 is shown. The signal WL&lt;0&gt; has a positive transition 32 which selects a wordline&lt;0&gt; and a negative transition 34 which deselects the wordline&lt;0&gt;. The signal WL&lt;m&gt; has a positive transition 36 which selects a wordline&lt;m&gt; and a negative transition 38 which deselects wordline&lt;m&gt;. The signal COL&lt;0&gt; has a positive transition 40 which selects a column&lt;0&gt; and a negative transition 42 which deselects the column&lt;0&gt;. The signal BL&lt;0&gt; has a negative transition 44 that responds to the positive transition 32 of the signal WL&lt;0&gt;. The signal TBUS &lt;0&gt; has a negative transition 46 that responds to the negative transition 44 of the signal BL&lt;0&gt;. A signal GREF has a constant voltage level 60, where the level is defined as the mid voltage between the high and low levels of the signal TBUS&lt;0&gt;. The signal SAOUT&lt;0&gt; has a negative transition 50 that responds to an event 48 (i.e., when the negative transition 46 of the signal TBUS&lt;0&gt; crosses a constant voltage level 60 of the signal GREF). The signal BL&lt;0&gt; has a positive transition 52 that responds to the negative transition 34 of the signal WL&lt;0&gt;. The signal TBUS&lt;0&gt; has a positive transition 54 that responds to the positive transition 52 of the signal BL&lt;0&gt;. The signal SAOUT&lt;0&gt; has a positive transition 58 that responds to an event 56 (i.e., when the positive transition 54 of the signal TBUS&lt;0&gt; crosses the constant voltage level 60 of the signal GREF). For this example, a memory cell located at the wordline&lt;0&gt; and column&lt;0&gt; generally holds a "0" while a memory cell located at the wordline &lt;m&gt;, column &lt;0&gt; holds a "1". Since the memory cell located at the wordline&lt;m&gt; and column&lt;0&gt; contains a "1" the signals BL&lt;0&gt;, TBUS&lt;O&gt; and SAOUT(0&gt; are generally not affected since the current state of these signals matches the state stored in the memory cell.
Referring to FIG. 3, a circuit 10' illustrates a local reference circuit that may be used in a memory. A number of local reference blocks 18a'-18n' are shown presenting an individual reference signal to each of the sense amplifiers 16a'-16n'.
Referring to FIG. 4, a timing diagram of the circuit 10' is shown. The various signals respond in a similar fashion to the timing diagram illustrated in FIG. 2.
Referring to FIG. 5, a circuit 10" is shown illustrating a dynamic voltage reference circuit that may be used in a memory. The circuit 10" comprises a memory array 12", a column select block 14", a sense amplifier block 16", a reference block 18" and an enable control block 20". The reference block 18" is shown between the memory array 12" and the column select block 14". The memory array block 12" receives inputs WL&lt;0:m&gt; and DWL. The memory array block 12" generates an output DWLOUT which is presented as an input to the enable block 20". The reference block 18" generally responds to a virtual ground signal (i.e., VG&lt;0:n&gt;) that is received from the column select block 14".
Referring to FIG. 6, a timing diagram of the circuit of FIG. 5 is shown illustrating a signal WL&lt;0&gt;, a signal WL&lt;1&gt;, a signal COL&lt;0&gt;, a signal VG&lt;0&gt;, a signal BL&lt;0&gt;, a signal BLREF&lt;0&gt;,a signal TBUS&lt;0&gt;, a signal TBREF&lt;0&gt;, a signal DWL, a signal DWLOUT, a signal SAEN and a signal SAOUT&lt;0&gt;. Consider a first cycle that occurs when the wordline signal WL&lt;0&gt; has a positive transition 60 which selects wordline&lt;0&gt; and a negative transition 62 which deselects wordline&lt;0&gt;. The signal COL&lt;0&gt; has a positive transition 68 which selects column&lt;0&gt; and a negative transition 70 which deselects column&lt;0&gt;. The signal VG&lt;0&gt; has a negative transition 76 that responds to the positive transition 68 of the signal COL&lt;0&gt;, and a positive transition 78 that responds to the negative transition 70 of the signal COL&lt;0&gt;.
The signal BLREF&lt;0&gt; has a negative transition 84 that responds to the negative transition 76 of the signal VG&lt;0&gt;. The signal BL&lt;0&gt; has a negative transition 86 that responds to the positive transition 60 of the signal WL&lt;0&gt;. The signal TBREF&lt;0&gt;has a negative transition 88 that responds to the negative transition 84 of the signal BLREF&lt;0&gt;. A signal TBUS&lt;0&gt; has a negative transition 90 that responds to the negative transition 86 of the signal BL&lt;0&gt;. The signal TBUS&lt;0&gt; and TBREF&lt;0&gt; cross at a location 94. The signal DWL has a positive transition 114 and a negative transition 116 which are synchronized with the positive and negative transitions 60 and 62 of the signal WL&lt;0&gt;, respectively. The signal DWLOUT has a positive transition 118 and a negative transition 120 that respond to positive and negative transitions 114 and 116 of the signal DWL, respectively. The signal SAEN has a positive transition 122 and a negative transition 124 that respond to the positive and negative transitions 118 and 120 of the signal DWLOUT, respectively.
In a pulsed WORDLINE scheme, in order to sense data correctly it is essential that positive transition 122 of the signal SAEN occur after the crossing event 94 of the signals TBUS&lt;0&gt; and TBREF&lt;0&gt;. The signal SAOUT&lt;0&gt; has a negative transition 126 that responds to the positive transition 122 of the signal SAEN. It may be noted from FIG. 6 that time elapses between the beginning of the negative transition 90 of the signal TBUS&lt;0&gt;and the crossing event 94 with signal TBREF&lt;0&gt;. The signal SAEN is not activated until after the crossing event 94 has occurred. It will be shown that the time elapsed results in an increased access time and decreases the overall performance of the design.
A typical pulsed wordline scheme initiates a negative transition 62 of the signal WL&lt;0&gt;, a negative transition 70 of the signal COL&lt;0&gt; and a negative transition 116 of the signal DWL which are in response to the positive transition 122 of the signal SAEN. An example of such a pulsed wordline scheme may be found in copending application Ser. No. 08/884,561, filed on Jun. 27, 1997, (Attorney Docket No. 016820.P207) entitled "READ ONLY/RANDOM ACCESS MEMORY ARCHITECTURE AND METHODS FOR OPERATING SAME", which is hereby incorporated by reference in its entirety or in co-pending application Ser. No. 08/884,581, filed on Jun. 27, 1997, (Attorney Docket No. 016820.P208) entitled "REFERENCE VOLTAGE GENERATOR FOR MEMORY DEVICE", which is hereby incorporated by reference in its entirety. The signal BLREF&lt;0&gt; has a positive transition 97 that responds to the positive transition 78 of the signal VG&lt;0&gt;. The signal BL&lt;0&gt; has a positive transition 96 that responds to the negative transition 62 of the signal WL&lt;0&gt;. The signal TBREF&lt;0&gt; has a positive transition 98 that responds to the positive transition 97 of the signal BLREF&lt;0&gt;. The signal TBUS&lt;0&gt;has a positive transition 100 that responds to positive transition 96 of the signal BL&lt;0&gt;. The signal DWLOUT has a negative transition 120 that responds to a negative transition 116 of the signal DWL. The signal SAEN has a negative transition 124 that responds to the negative transition 120 of the signal DWLOUT. The signal SAOUT&lt;0&gt; does not transition relative to the negative transition 124 of the signal SAEN because the state of SAOUT&lt;0&gt; is latched after the positive transition 122 of the signal SAEN occurs. The state of the signal SAOUT&lt;0&gt; cannot change until another positive transition 136 of the signal SAEN occurs.
A second cycle begins with a positive transition 64 of the signal WL&lt;1&gt; and a positive transition 72 of the signal COL&lt;0&gt;. The positive transition 72 of the signal COL&lt;0&gt; causes a negative transition 80 of the signal VG&lt;0&gt;. The signal BLREF&lt;0&gt; has a negative transition 104 that responds to the negative transition 80 of the signal VG&lt;0&gt;. The signal TBREF&lt;0&gt; has a negative transition 106 that responds to the negative transition 104 of the signal BLREF&lt;0&gt;. The signal DWLOUT has a positive transition 132 that responds to a positive transition 128 of the signal DWL, where the positive transition 128 and negative transition 130 of the signal DWL is synchronized with the positive transition 64 and negative transition 66 of the signal WL&lt;1&gt;, respectively. The signal SAEN has a positive transition 136 that responds to the positive transition 132 of the signal DWLOUT. The signal SAOUT&lt;0&gt; has a positive transition 140 that responds to the positive transition 136 of the signal SAEN.
The pulsed WORDLINE scheme initiates a negative transition 66 of the signal WL&lt;1&gt;, a negative transition 74 of the signal COL&lt;0&gt; and a negative transition 130 of the signal DWL each in response to the positive transition 136 of the signal SAEN. The signal VG&lt;0&gt; has a positive transition 108 that responds to the negative transition 74 of the signal COL&lt;0&gt;. The signal BLREF&lt;0&gt;has a positive transition 110 that responds to the positive transition 108 of the signal VG&lt;0&gt;. The signal TBREF&lt;0&gt; has a positive transition 112 that responds to the positive transition 110 of the signal BLREF&lt;0&gt;. The signal DWLOUT has a negative transition 134 that responds to the negative transition 130 of the signal DWL. The signal SAEN has a negative transition 138 that responds to the negative transition 134 of the signal DWLOUT. The disadvantage of the reference scheme shown in FIG. 5 and FIG. 6 is related to when the signal SAEN is activated. In FIG. 6, the positive transition 122 of the signal SAEN cannot occur until after the event 94 occurs. Additional delay measured from the beginning of the negative transition 90 of the signal TBUS&lt;0&gt; to the crossing event 94 is required in order to sense and latch the correct state.
Referring to FIG. 7, a diagram of a portion of the reference block 18" of FIG. 5 including two memory cells from a portion of the memory array block 12" of FIG. 5 is shown. The portion of the reference block 18" generally comprises a transistor 120, a transistor 122, a transistor 126, a transistor 128, a transistor 130 and a transistor 132. The transistors 124 and 134 generally represent memory cells that are connected between the signal WL and the virtual ground line VG&lt;0:1&gt; and the bitline BL&lt;0:1&gt;.
Referring to FIG. 8, a timing diagram of the wordline WL, the virtual ground line VG&lt;0:1&gt; and the bitline BL&lt;0:1&gt; of FIG. 7 is shown. The negative transition 84 of the signal BL&lt;1&gt; shows a time difference .DELTA.T prior to the negative transition 86 of the signal BL&lt;0&gt;. In the first cycle the signal BL&lt;1&gt; acts as the reference and in the second cycle, the signal BL&lt;0&gt; acts as the reference.